The present invention specifically relates to interconnect structures for microelectronics, e.g., in the packaging of microelectronic units such as integrated circuits (“ICS” or “chips”) and other interconnect structures, e.g., circuit panels such as printed which may include wiring boards.
In some multi-layer wiring boards, a heat-curable resin such as an epoxy resin is used as an insulator within each wiring level. Interconnections are patterned after a curing reaction performed while the cured substrate is held tightly in a fixture. In this way, interconnections do not twist or break as a result of joining the wiring levels and insulators together in one multilayer board.
Unfortunately, when wiring levels of a multilayer wiring board are insulated by a thermoplastic, presently available methods produce unsatisfactory results. The thermoplastic insulators of each level are joined at temperatures near the melting point of the thermoplastic resin. This causes the metal interconnects within such multilayer wiring boards to twist, short with adjacent interconnections, break, or the like.
In such boards, because the metal interconnect layer protrudes above the surface of each interlayer insulation layer, there was a tendency to have indentations and protrusions on the surfaces of the wiring board layers that make up the multilayer wiring board. When multilayer wiring boards are produced through joining together a plurality of these wiring board layers, the greater the number of layers, the larger the indentations and protrusions on the surface of the multilayer wiring boards. Given this, as wiring boards, the interconnection patterns could become distorted, the adjacent interconnections could short to each other, interconnections could break, and the like, producing fatal defects. In addition, electronic components mounted to such multilayer wiring boards, such as semiconductor integrated circuits, large-scale integrated circuits, and the like, in particular, have large numbers of small terminals. Accordingly, it is highly desirable to maintain the planarity of each set of metal interconnects on an interconnect element or multilayer wiring board. In some cases, large deviations from planarity of the surface of interconnect element on which electronic components such as a chip is mounted is an impediment to high-reliability mounting.
Consequently, excessive indentations and protrusions on the surface of a multilayer wiring board causes problems that cannot be ignored, and thus must be eliminated.
Secondly, given the conventional technology described above, the production of a single multilayer wiring board can require layering process in which one wiring board is joined to another wiring board and in which another wiring board is then joined to the layered unit produced by the prior joining process. This process would then be repeated multiple times, resulting in many manufacturing steps for the multilayer wiring board, making reductions in manufacturing costs difficult.